This application claims benefit of priority under 35 U.S.C. xc2xa7119 to Japanese Patent Application No. H11-67441, filed on Mar. 12, 1999, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates generally to a nonvolatile semiconductor memory device, and a method for producing the same. More specifically, the invention relates to a nonvolatile semiconductor memory device having a stacked gate type transistor, and a method for producing the same.
2. Description of the Related Background
A typical nonvolatile semiconductor memory device is provided with a cell transistor forming region for forming a cell transistor for nonvolatilisably accumulating charges, a selecting transistor forming region for forming a selecting transistor for selectively operating the cell transistor, and a peripheral transistor forming region for forming a peripheral transistor for the cell transistor and the selecting transistor.
The cell transistor has a two-layer structure which comprises a first polysilicon layer constituting a floating gate, and a second polysilicon layer constituting a control gate. Therefore, in order to flatten the surface of a nonvolatile semiconductor memory device, it is desired that the peripheral transistor and the selecting transistor have a two-layer structure. That is, it is desired that the height of the cell transistor in the cell transistor forming region is the same as the height of the selecting transistor in the selecting transistor forming region. Moreover, it is desired that the height of the cell transistor in the cell transistor forming region is the same as the height of the selecting transistor in the peripheral transistor forming region.
According to one aspect of the present invention, a method for producing a nonvolatile semiconductor memory device comprising: a cell transistor which is formed on a semiconductor substrate and which has a cell insulator film, a floating gate, a first intergate insulator film, a control gate and a cell mask film; and a transistor which is formed on said semiconductor substrate and which has a transistor insulator film, a first gate electrode, a second intergate insulator film, a second gate electrode and a transistor mask film, said method comprising:
sequentially forming a first insulator film, a first conductive film, a second insulator film, a second conductive film and a mask film on a semiconductor substrate;
patterning said mask film to form said cell mask film and said transistor mask film;
etching said second conductive film and said second insulator film using said cell mask film and said transistor mask film as masks to form said control gate and said second gate electrode and to form said first intergate insulator film and said second intergate insulator film;
forming a resist pattern so that a part of said resist pattern overlaps with said transistor mask film; and
etching said first conductive film using said cell mask film, said transistor mask film and said resist pattern as masks to form said floating gate and said first gate electrode.
According to another aspect of the present invention, a nonvolatile semiconductor memory device having a cell transistor and a non-cell transistor which are covered with an interlayer insulator film, wherein said non-cell transistor comprises:
a first insulator film formed on a semiconductor substrate;
a first gate electrode formed on said first insulator film;
a second insulator film formed on said first gate electrode in a first area of said gate electrode, said first area being a part of said first gate electrode;
a second gate electrode formed on said second insulator film; and
a contact portion embedded in a contact hole of said interlayer insulator film to contact said first gate electrode in a second area of said first gate electrode, wherein said second insulator film is not formed on said second area and said contact portion is out of contact with said second insulator film.